The client required full-chip verification for a complex GPU/CPU SoC to ensure functionality, low-power operation, and interface protocol validation before silicon tape-out.
✔︎ Full-chip SoC verification
✔︎ Low-power validation (UPF)
✔︎ UVM-based testbench development
The client required rigorous verification of a Secure Boot Unit to ensure security integrity and low-power functionality across multiple power domains within a complex SoC architecture.
✔︎ Formal verification methodology
✔︎ UPF-based low power validation
✔︎ Assertion and connectivity checks
The client required system-level validation of high-speed interfaces using Veloce models to ensure protocol compliance and seamless FPGA bring-up across complex SoC subsystems.
✔︎ Veloce model validation
✔︎ PCIe4, NoC & LPDDR4/5 protocol testing
✔︎ FPGA bring-up with PureSim & softmodel flows
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