PCIe4 / NoC / LPDDR4/5 Veloce Model Validation

A leading semiconductor company developing high-performance SoC platforms required advanced validation of critical interconnect and memory subsystems before silicon tape-out. The project focused on validating complex protocols including PCIe Gen4, Network-on-Chip (NoC), and LPDDR4/5 memory interfaces using Veloce emulation models.

The objective was to develop scalable validation models that could support system-level testing, protocol compliance verification, and early FPGA bring-up, enabling faster design validation and reduced risk during silicon implementation.

Our engineering team created robust Veloce-based validation environments integrating transactor libraries, custom DDR/DFI support, and advanced testbench architectures. This enabled comprehensive protocol validation across simulation, emulation, and FPGA-based prototyping environments.

The Chalange

Modern SoCs integrate multiple high-speed interfaces and memory subsystems that must operate seamlessly together under complex workloads. Ensuring protocol correctness and system-level stability required advanced validation methodologies.

Key challenges included:

• Validating PCIe Gen4 interface functionality and protocol compliance

• Ensuring reliable Network-on-Chip (NoC) communication across system components

• Verifying LPDDR4/LPDDR5 memory subsystem behavior

• Developing scalable Veloce validation models using transactor libraries

• Supporting FPGA bring-up using PureSim and softmodel flows

• Creating advanced test scenarios for system-level performance and stress testing

Additionally, the validation framework needed to enable efficient debugging, system-level visibility, and correlation between simulation and emulation environments.

Our Solution

Our validation engineers developed a comprehensive validation framework leveraging Veloce emulation platforms and advanced testbench methodologies.

Veloce Model Development

Dual-top Veloce models were developed to integrate PCIe, NoC, and LPDDR subsystems within a unified validation environment. These models enabled high-speed emulation and accelerated verification cycles.

Protocol Validation

Dedicated validation scenarios were created to test PCIe Gen4, NoC, and LPDDR4/5 protocol behavior across multiple operating conditions. This ensured protocol compliance and reliable subsystem communication.

DDR/DFI Test Support

Custom DDR/DFI test support was implemented to validate memory controller functionality and ensure reliable interaction with LPDDR memory devices.

FPGA Bring-Up Enablement

Validation environments supported FPGA bring-up using PureSim and softmodel flows, enabling early hardware validation and faster system integration.

Advanced Test Development

Engineers developed advanced UVM-based testcases to validate system-level scenarios, enabling deep protocol validation and correlation between simulation and emulation environments.

The Results

• Successful system-level validation of PCIe4, NoC, and LPDDR4/5 interfaces
• Development of scalable Veloce validation models
• Reliable FPGA bring-up using PureSim and softmodel flows

• Comprehensive protocol validation across simulation and emulation platforms
• Enhanced system visibility for debugging and performance analysis

Technology Used

Veloce Emulation Platform
PCIe Gen4 Protocol
Network-on-Chip (NoC)
LPDDR4 / LPDDR5
DDR / DFI Interface Testing
UVM (Universal Verification Methodology)
FPGA Bring-Up
PureSim & Softmodel Flows