The Angstrom Era: GAAFETs, 2nm Scaling, and the Future of Chip Power

The End of the Road for FinFETs

For over a decade, the familiar Fin Field-Effect Transistor (FinFET) architecture served as the essential engine of Moore’s Law, allowing the semiconductor industry to shrink components while controlling leakage current.³ However, in the high-stakes race to build the next generation of processors for AI, high-performance computing (HPC), and mobile devices, the FinFET design has hit an unyielding physical wall.⁴

To make a FinFET device faster, engineers had to add more parallel fins, which inherently consumed valuable lateral area—a scaling constraint that limited true miniaturization.⁵ This is why the industry is undergoing a revolutionary architectural shift away from the familiar “nanometer” label (a marketing term for a generation of improvement, not a literal measurement ⁶) and into the Angstrom Era (2nm is 20 Angstroms).⁴ This shift is defined by the necessary adoption of the Gate-All-Around FET (GAAFET).⁵

The Core Breakthrough: Gate-All-Around (GAAFET)

The transition to 2nm process technology is fundamentally a move to the GAAFET structure, which is widely considered the “ultimate CMOS device in terms of electrostatics”.⁴

Unlike a FinFET, where the gate surrounds only three sides of the channel, a GAAFET completely encloses the entire channel.⁵ This simple yet profound change allows the gate to regain robust electrostatic control, effectively suppressing leakage currents—a persistent problem as transistors shrink.⁷

GAAFETs are often implemented using stacked nanosheet or nanowire technology.⁵ This nanosheet approach offers two crucial benefits over FinFETs:

1. Higher Drive Current: The nanosheets deliver a larger drive current, which translates directly into faster switching speeds and better performance.⁵
2. Area Efficiency: Nanosheets are stacked vertically, eliminating the need to add horizontal fins to increase speed. This achieves higher speed within a smaller overall footprint.⁵

Leading foundries are implementing their own flavors of this technology: Intel calls its GAAFET implementation RibbonFET (used at its 18A node), and Samsung deployed its variant, the Multi-Bridge Channel FET (MBCFET), at the 3nm node.⁸

The Hidden Hero: Backside Power Delivery (BSPDN)

The performance gains at 2nm are not just about the transistor; they are equally reliant on radical re-engineering of the chip’s foundation. This is where the Backside Power Delivery Network (BSPDN) comes into play.⁹

In traditional chips, power and signal lines compete for space on the top (front side) of the wafer. As density increases, this competition leads to poor power stability and resistance.⁹ BSPDN resolves this by routing the power supply network through the backside of the wafer, separating it from the signal network.⁹

This architectural shift offers dramatic gains:

• Area Reduction: By utilizing the backside, the critical frontside area is freed up for more complex signal routing and additional transistors. Samsung anticipates that BSPDN will cut the size of its 2nm chips by a considerable 17%.¹⁰
• Efficiency: Power is delivered over the shortest possible distance to the transistors, improving overall power transmission efficiency.⁹

The successful adoption of GAAFETs alongside BSPDN confirms that modern scaling is not just about shrinking; it’s about System-Technology Co-Optimization (STCO)—optimizing devices, interconnects, and packaging simultaneously.⁸

The Foundry Race: Battle for the Angstrom Era

The 2nm competitive landscape is intense, with major foundries targeting 2025 for mass production of their Angstrom-era nodes.⁶

Foundry Node	Architecture	Key Targets (vs. Previous Node)	Production Timeline
Intel 18A	RibbonFET (GAA) + PowerVia (BSPDN)	Up to 25% higher frequency (iso-voltage) or 38% power savings (iso-clock) 11	Enablement H1 2024 (aggressive) 6
TSMC N2	GAAFET Nanosheet + BSPDN	10–15% higher performance (iso-power) or 20–30% lower power (iso-performance) 6	Mass Production H2 2025 6
Samsung 2GAP (SF2)	MBCFET (GAA Variant) + BSPDN	Projected 17% chip size reduction via BSPDN 10	Production in 2025 6

While Intel has set aggressive performance targets, TSMC retains its advantage in reputation for reliable, high-volume manufacturing.⁸ Regardless of the winner, success relies on deploying these complex technologies, including highly advanced High Numerical Aperture (High-NA) Extreme Ultraviolet (EUV) lithography, which costs nearly $380 million per tool.¹²

Beyond 2nm: The Vertical Future with CFETs

As the industry looks ahead, the roadmap confirms that the future of scaling is decisively vertical.⁷ The next major architectural leap will be the Complementary FET (CFET), slated for deployment around the A7 (1.8nm) node.⁷

CFETs solve the last major lateral area constraint of CMOS design by vertically stacking the nFET (negative channel) devices directly on top of the pFET (positive channel) devices.¹³ This “folding” eliminates the space previously required to separate the two types of transistors, achieving maximum density and paving the way for further gains through three-dimensional integration and advanced packaging techniques.¹³

The shift to 2nm and beyond is more than a simple node shrink; it is a total architectural overhaul—a “sum of several ‘Aha!’ moments”—that ensures silicon can continue to power the escalating demands of the digital world for years to come.¹⁵

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Works cited

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